In recent years, every time a company expands its business due to the company growth, the company has been required to improve the processing performance of a server apparatus. Types of means for developing a computing processing performance of a server apparatus of the related art can be roughly categorized into two types, i.e., “scale out” and “scale up.”
As represented by a blade server, the scale out method is means for developing a computing processing performance of a server by adding a server module. A set of a CPU, a main memory, an HDD, and an I/O is considered as a set of server modules. The scale out method is effective when many processes which have a slight relevance with each other are present. While there is an advantage that the development is easily possible by adding the server modules, there is a problem that the method may not be adopted when an especially high processing performance, such as a certain degree of batch processing is required.
Alternatively, as represented by a large scale SMP structure, the scale up method is means for developing and improving the processing performance of a server itself by increasing the speed of a processor, adding a processor, and increasing the capacity of a memory. While the scale up method is effective when an especially high processing performance, such as a large scale batch processing is required, there is a problem that the large scale SMP is generally expensive, and huge costs may be incurred when introducing the system and further developing the system after the introduction.
To solve the above problems, PTL 1 describes a technique for an SMP connection among a plurality of blade server modules, and provides a server apparatus that includes, in addition to a scale out type development performance of a blade server system of the related art, a scale up type development performance. Use of this technique allows developing the system by adopting either one of the scale out type and the scale up type, only for capability necessary in a server module unit of the CPU, the main memory, the HDD, and the I/O.
Further, PTL 2 provides a detachable SMP connection device (frontplane) to be mounted on a blade server module in place of wiring of the SMP connection through a backplane in order to realize SMP among server modules.
However, both of PTL 1 and PTL 2 only describe the technique of the SMP connection between CPUs of different server modules. Thus, if the techniques described in PTL 1 and PTL 2 are used to develop the scale up type system, the number of HDDs is increased in a server module unit. As a result, an operation system (OS) cannot recognize the HDDs as a single disk. Therefore, there is a problem that it is difficult to combine HDDs that are included over the server modules to configure RAID, and the HDDs in the system may not be effectively used.
FIG. 6 illustrates an exemplary system apparatus configured by using the related art.
An information processing apparatus 600a includes a CPU 601a, a main memory 602a, a PCI Express root port 603a, a storage device controller 604a, a board management controller (BMC) 605a, an FPGA 606a, an HDD 607a, and an HDD Status LED 608a that indicates the status of the HDD.
The BMC in the information processing apparatus is connected to a system control controller 619 in a system apparatus control module 618 through a transmission path 617a via a backplane 620.
The HDD 607a in the information processing apparatus is connected to a port 610a for connection with an HDD in the storage device controller 604a through a transmission path 609a. 
The storage device controller includes a plurality of input-output terminals represented by a general-purpose input/output (GPIO) pin usable for various purposes depending on setting. As an example, in the storage device controller illustrated in FIG. 6, a purpose of a GPIO 611a is set as an LED control. The GPIO 611a is connected to the Status LED 608a in the information processing apparatus through a sideband signal 612a. Accordingly, an LED that indicates the status of the HDD is controlled.
Similarly, in the storage device controller, a purpose of a GPIO 613a is set as an HDD Presence recognition. The GPIO 613a is connected to the HDD 607a through a sideband signal 614a. Accordingly, the storage device controller recognizes whether the HDD is mounted or not.
A similar information processing apparatus (information processing apparatus 600b) is present. Similarly to the BMC 605a, a BMC 605b in the information processing apparatus 600b is also connected to the system control controller 619 through a transmission path 617b via the backplane.
By connecting a frontplane 615, CPUs (601a and 601b) in the two information processing apparatuses (600a and 600b) are connected to each other through a transmission path 616. Thus, the SMP connection between the CPUs becomes possible. Accordingly, a plurality of information processing apparatuses is capable of operating as a single system apparatus.
On the other hand, the HDD 607a in the information processing apparatus 600a is connected to the storage device controller 604a. Similarly, an HDD 607b in the information processing apparatus 600b is connected to a storage device controller 604b. Therefore, the OS cannot recognize the plurality of HDDs as a single disk.
The example of FIG. 6 illustrates an information processing apparatus mounted with only one HDD. However, there is the following problem with a system in which each of two information processing apparatuses includes two HDDs, and such two information processing apparatuses are combined to configure the SMP. That is, in a current condition, the RAID is configured for each information processing apparatus. Thus, even though four HDDs are present in the system, only RAID0 or RAID1 can be set for each information processing apparatus.